1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device which has a metallic silicide layer.
2. Description of the Related Art
In a method for fabricating a semiconductor process, a metallic silicide layer is used for a gate electrode, an active region or conductive line in order to lower resistance.
A self-aligned silicide (SALICIDE) method is well known as a method for forming the metallic silicide layer. In the SAUCIDE method, first a metallic layer, such as a cobalt layer is formed on a substrate, and then plural heat treatments are carried out. Generally, a first heat treatment is for forming a metallic silicide in a surface of the substrate by diffusing a material of the metallic layer into the substrate. Other heat treatments are for reducing a resistance of the metallic silicide layer. Thereby, the metallic silicide layer can be formed in predetermined portions in the substrate by a self-aligned method.
Such SALICIDE method is disclosed in Japanese Laid-Open Patent Publication:HEI10-45416, published on Feb. 17, 1998. An outline of the process in the publication is shown in FIGS. 7(A)-(D). The corresponding method for forming a cobalt silicide layer is described hereinafter.
Active regions 103a and 103b, a gate electrode 105, side walls 107 which are formed on the sides of the gate electrode 105 and a field insulating layer 109 are formed on a semiconductor substrate 101, as shown in FIG. 7(A). These elements are defined as abase 111.
A cobalt layer 113 is formed on the base 111 by a sputtering method, as shown in FIG. 7(B).
Then, a first heat treatment is carried out That is, the base 111 on which the cobalt layer 113 is formed, is heated to a temperature within a range of 450.degree. C..about.500.degree. C. by alamp anneal, as shown in FIG. 7(C). Thereby, cobalt sihicide layers are formed in interface surfaces. The cobalt silicide layers 115a, 115b, 115c are respectively formed on the interface surfaces between the cobalt layer 113 and the active regions 103a, 103b and the gate electrode 105. Such cobalt silicide layers 115a, 115b, 115c are composed of a CoSi layer which has a composition ratio of cobalt and silicon that is 1:1 or a Co.sub.2 Si layer which includes more cobalt than silicon. So, resistivity of the cobalt silicide layers 115a, 115b, 115c is high.
Then, the cobalt layer 113 on the semiconductor substrate 101 is removed by a wet-etching method, as shown in FIG. 7(D).
Then, a second heat treatment is carried out. That is, the cobalt silicide layers 115a, 115b and 115c are heated to a temperature within a range of 650.degree. C..about.900.degree. C. by the lamp anneal. This temperature is higher than that of the first heat treatment. Thereby, the CoSi layer or the Co.sub.2 Si layer of the cobalt silicide layers 115a, 115b and 115c are changed into a CoSi.sub.2 layers. Therefore, as resistivity of the cobalt silicide layers 115a, 115b, 115c become low, resistance of the gate electrode 105 and the active regions 103a, 103b can be reduced.
However, in such a method, crystallization of Co.sub.2 Si in the cobalt silicide layers partially grows up during the second heat treatment which is carried out at the high temperature. That is, after the second heat treatment for reducing the resistance, large crystallization partially exists in the cobalt silicide layers. As a result, evenness of the cobalt silicide layers is markedly deformed.
FIG. 8(A) and FIG. 8(B) illustrate an outline of the unevenness of the cobalt silicon layers. FIG. 8(A) shows the cobalt silicide layers after the second heat treatment. FIG. 8(B) shows contacting holes which are formed in an intermediate insulating layer on the cobalt silicide layers after the second heat treatment.
As shown in FIG. 8(A), evenness of the cobalt silicide layers is deformed by the large crystallization which is formed by the second heat treatment. That is, surfaces of the cobalt silicide layers 119a, 119c and interfaces between the cobalt silicide layer 119a and the active regions 103a are uneven. A dip 121 in which the surface of the cobalt silicide layer 119a sags partially, a discontinuous portion 123 in which the surface of the cobalt silicide layer 119c is partially disconnected, and a coarse large crystallization 125 which reaches to the substrate 101 through the active region 103a by growing of the large crystallization are shown in FIG. 8(A). The coarse large crystallization 125 causes a leakage current between the substrate 101 and a conductive line which is formed thereafter.
Generally, contacting holes 129 are formed in an intermediate insulating layer 127 on the cobalt silicide layers. If the contact hole 129 is formed on the dip 121, the substrate 101 is over-etched by an etching process which is used for the contacting hole 129. Therefore, a leakage current between the substrate 101 and a conductive line which is formed in the contacting hole 129 occurs. Further, as the discontinuous portion 123 increases a resistance, a defective connection to the contacting hole results.
Such effects are not limited to cobalt silicide layers, but also occur when metals, such as platinum or titanium are used for forming a metallic silicide. In particular, in the case where a silicon on insulator (SOI) substrate which has an insulating film and a thin silicon film formed on a substrate is used as the substrate, the thin silicon film is very thin. The thin silicon film is easily over-etched while forming the contacting holes, resulting in a defective connection at the contacting hole and a leakage current.
Thus, in the conventional method for forming the metallic silicide layer, as evenness of the metallic silicide layer is deformed, leakage current and defective connections become considerable problems.